In this paper, an enhanced Self-checking carry select adder (CSeA) architecture is introduced. However, we first show that the carry select adder design presented literature does not have the Self-checking property in all of its parts in spite of the stated claim. Then, we present a corrected design with the Self-checking property that requires more overheads. In addition, we reveal some mistakes in reporting the transistor count of the proposed design in the literature in different sizes, and correct them which again leads to more transistor count and overhead. At the end, due to the fact that the performance of a CSeA depends on its grouping structure, the area overheads of different CSeAs including the corrected designs and the best of previous Self-checking designs will be evaluated with respect to the same-size and different-size grouping structures. These evaluations show the comparison of different CSeAs, more appropriate compared to the previous evaluations.

Today, the use of CMOS technology for the manufacture of electronic ICs has faced many limitations. Many alternatives to CMOS technology are offered and made every day. Quantum-dot cellular automata (QCA) is one of the most widely used. QCA gates and circuits have many advantages including small size, low power consumption and high speed. On the other hand, using special digital gates called reversible gates, a series of reversible circuits can be built that have their own advantages and applications in digital design. Reversible circuits can be implemented by QCA gates. One of the most important reversible gates implemented by QCA gates is QCA1 gate. In this paper we have proposed a reversible full adder using QCA1 gates which has fault-tolerant structure. This structure has better indexes such as area and latency than similar ones. Reversible circuits are a kind of intelligent systems; because the possible system error can be distinguished by the output values.

Differential Cascode Voltage Switch (DCVS) is one of the most well-known logic styles, which forms a robust structure. In addition, two complementary outputs are produced in this logic style at the same time. It has several unique attributes and different applications. This paper presents three comparable methods to design some ternary half adders, whose efficiencies are superior especially when they are put one after another in a cascading scenario. These cells are essential for the realization of larger arithmetic circuits. In the third proposed method, instead of ternary inverters, which consume considerable static power, built-in low-power binary boosters are exploited to reinforce driving power of the DCVS circuits. Simulation results by HSPICE and 32 nm Carbon Nanotube Field Effect Transistor (CNFET) technology demonstrate that the new adder cell with binary boosters operates 21. 8% faster and consume 6. 7% less power than the cell with ternary inverters in a real test bed. Furthermore, the final design is compared with three other ternary half adders. The new design is faster than all of them, and also consumes less power and energy than the previous DCVS half adder.

In this paper, the design of penternary circuits based on graphene nanoribbon FET (GNRFET) is presented. The employed logic of the penternary corresponds to the Galois logic. The HSPICE-compatible model and 15-nanometer technology have been used to simulate the graphene nanoribbon transistor. Accordingly, the proposed NAND and NOR penternary circuits are first, designed and simulated. The results show that these proposed circuits have a significant improvement in terms of speed and power consumption compared to their CNTFET counterparts. Then, the adder circuit as the main part of digital processors in integrated circuit design is proposed with penternary logic. The transient responses of the proposed circuits are accurate. Parameters such as power consumption, , delay and power-delay product are calculated. Evaluation of the results shows that the proposed adder circuit has the power-delay product (PDP) of 179. 39 fJ at the supply voltage of 0. 8 V and the operating frequency of 100 MHz.